1. Field of the Disclosure
The present disclosure relates to electronic devices and processes, and more particularly to electronic devices including static-random-access memory cells and processes of forming the electronic devices.
2. Description of the Related Art
Static-random-access memory (“SRAM”) cells are commonly used within integrated circuits as stand alone memories or as a memory array within a microcontroller, microprocessor, or other electronic device. FIG. 1 includes a circuit schematic for a six-transistor SRAM cell 100. A bit line 112 is electrically connected to a source/drain (“S/D”) region of a pass gate transistor 122. As used herein, S/D region will be used to refer to a region that can act as a source region, a drain region, or a region that can act as a source or drain, depending on biasing conditions. Another S/D region of pass gate transistor 122 is electrically connected to S/D regions of a pull-down transistor 124 and a pull-up transistor 126 and to gate electrodes of a pull-down transistor 144 and a pull-up transistor 146. The node, which is formed by the electrical connections between the S/D regions of transistors 122, 124, and 126 and the gate electrodes of transistors 144 and 146, is a storage node of the SRAM cell 100.
A S/D region of pass gate transistor 142 is electrically connected to a different bit line 132. During the write operation and at the end of the read operation of the memory cell 100, the signal on the bit line 132 is complementary to the signal on the bit line 112. Bit line 112 or 132 may be referred to as BL, and the other bit line 112 or 132 may be referred to as BL bar. For example, if the signal on bit line 112 has a value corresponding to “high” or “1”, the signal on bit line 132 typically has a value of “low” or “0” during the write operation or at the end of the read operation. Another S/D region of the pass gate transistor 142 is electrically connected to S/D regions of the pull-down transistor 144 and the pull-up transistor 146 and to gate electrodes of the pull-down 124 and the pull-up transistor 126. The node, which is formed by the electrical connections between the S/D regions of the transistors 142, 144, and 146 and the gate electrodes of the transistors 124 and 126, is another storage node of the SRAM cell 100.
The gate electrodes of pass gate transistors 122 and 142 are electrically connected to a word line 152. Other S/D regions of the pull-down transistors 124 and 144 are electrically connected to a VSS line 154, and other S/D regions of pull-up transistors 126 and 146 are electrically connected to a VDD line 156. Typically, transistors 122, 124, 142, and 144 are n-channel transistors, and transistors 126 and 146 are p-channel transistors.
Semiconductor-on-insulator (“SOI”) technology can be used in forming memory cells. FIG. 2 includes an illustration of a layout of active regions and conductive members that may be used for an SRAM cell. As used throughout this specification, insulating layers are not illustrated in top views to simplify understanding of the positional relationships of features to one another.
FIG. 2 includes semiconductor fins 222, 224, 226, and 228 that overlie a base material 202 (e.g., a semiconductor wafer). In FIG. 2, the semiconductor fins 222, 224, 226, and 228 are patterned such that they extend in vertical directions as illustrated in FIG. 2. Conductive members 242, 244, 246, and 248 extend in horizontal directions as illustrated in FIG. 2 and overlie portions of the semiconductor fins. Portions of the conductive members 242, 244, 246, and 248 include gate electrodes where those conductive members lie adjacent to the semiconductor fins. Locations of transistors 122, 124, 126, 142, 144, and 146 are illustrated in FIG. 2.
The semiconductor fin 224 has a portion that is electrically connected to the conductive member 244 at contact 254, and the semiconductor fin 226 is electrically connected to the conductive member 246 at contact 256. Although not illustrated, other contacts and conductive members or other interconnects can be formed to complete the electrical connections to achieve and SRAM cell. For example, the conductive members 242 and 248 may be connected to an overlying conductive member (not illustrated) that forms part of the word line 152. Another overlying conductive member (not illustrated) may be formed at the same level to complete the electrical connections for the storage nodes of the SRAM cell. Other conductive members or interconnects can be formed to make the connections to the bit lines 112 and 132, the VSS line 154, and VDD line 156.
By using rectilinear patterns for the features within the SRAM cell, as illustrated in FIG. 2, the SRAM may occupy too much area, and thus lower the memory cell density within a memory array. In addition, the transistors have channel lengths that lie long substantially parallel lines that are typically along a (100) or (110) crystal plane. Regarding the (100) and (110) crystal planes, those crystal planes intersect at 45° when the primary surface a semiconductor layer lies along a (100) or (110) crystal plane. Electron mobility is higher along a (100) crystal plane, as opposed to a (110) crystal plane, and hole mobility is higher along a (110) crystal plane, as opposed to a (100) crystal plane. The electronic characteristics for the transistors may not be optimized for use within the SRAM cell.
One or more of the semiconductor fins could include portions that lie along different lines that intersect at angles that are integer multiples of 22.5° (e.g., 0°, 22.5°, 45°, 67.5°, etc.). While angles can be integer multiples of 22.5°, the use of discrete values for the angles still may limit how much the area of the memory cell can be reduced, may not allow the electronic performance of the SRAM cell to be optimized, or both.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.